1. Field of the Invention
The present invention relates to a code modulator and a code modulation method, particularly to a modulator and a modulation method for modulating input codes on the basis of a table in which modulation codes corresponding to input codes are stored, and more particularly to a modulator and a modulation method for modulating codes to be written in optical disks such as DVDs (Digital Video Disks).
2. Description of Related Art
In order to modulate code in a DVD, a modulation system referred to as an 8/16 modulation is used. The 8/16 modulation converts an 8-bit input code into a 16-bit code, and records the converted 16-bit code in succession to a 16-bit code obtained by converting the immediately previous input code. The code forms a bit string of bits having a xe2x80x9c0xe2x80x9d value and bits having a xe2x80x9c1xe2x80x9d value. In the bit string, the minimum number of bits having a xe2x80x9c0xe2x80x9d value positioned between two bits having a xe2x80x9c1xe2x80x9d value is defined as 2 and the maximum is defined as 10, which is hereinafter referred to as RLL (2.10) requirements. Note that RLL is an abbreviation for Run Length Limited. The conversion of an 8-bit code to a 16-bit code is carried out on the basis of a conversion table in which conversion codes corresponding to input codes are stored.
FIG. 10 shows a structural example of a code modulator 80 for executing the 8/16 modulation. This modulator 80 converts an 8-bit (0 to 255) input code to a 16-bit code, and includes a conversion table 84 and a code conversion section 82.
The conversion table 84 includes a main table and a sub-table. As shown in FIG. 11, the main table stores a plurality of conversion codes (STATE 1, 2, 3, 4) corresponding to respective input codes of 0 to 255. As shown in Table 12, the sub-table stores a plurality of conversion codes (STATE 1, 2, 3, 4) corresponding to respective input codes of 0 to 87. Normally, a ROM (Read Only Memory) is used as the conversion table 4.
A value NS (NS=1, 2, 3 or 4) is added to each conversion code. When a conversion code is used in a conversion of an input code, the value NS indicates a STATE of a conversion code that is used for the conversion of the next input code. For example, in the case where a conversion code having an input of 255 and a STATE of xe2x80x9c3xe2x80x9d is used, the NS value of that conversion code is xe2x80x9c2xe2x80x9d. Therefore, in the next input (for example, 89) code conversion, the conversion code having an input of 89 and a STATE of xe2x80x9c2xe2x80x9d is used.
Next, an explanation of the next STATE (NS) and respective conversion codes will be given. In this embodiment, where the last bit or the last two bits of the conversion code used in an input code conversion is/are xe2x80x9c1xe2x80x9d or xe2x80x9c1 0xe2x80x9d, a conversion code of STATE 1 is designated as the conversion code used for the next code conversion. In this case, in order to satisfy the RLL (2.10) requirements, the first two bits to nine bits of bit string of the conversion code of STATE 1 are continuous xe2x80x9c0xe2x80x9ds.
Where last two bits to five bits of the conversion code used in an input code conversion are continuous xe2x80x9c0xe2x80x9ds, a conversion code of STATE 2 or STATE 3 is designated as the conversion code used for the next code conversion in this embodiment. In order to satisfy the RLL (2.10) requirements, the first bit of the conversion codes of STATE 2 and STATE 3 are xe2x80x9c1xe2x80x9d or the first five bits of the conversion codes of STATE 2 and STATE 3 are continuous xe2x80x9c0xe2x80x9ds. In this case, the first bit and the 13th bit of the conversion code of STATE 2 are always xe2x80x9c0xe2x80x9d, and the first bit and/or the 13th bit of the conversion code of STATE 3 is/are always xe2x80x9c1xe2x80x9d.
Where the last six bits to nine bits of the conversion code used in an input code conversion are continuous xe2x80x9c0xe2x80x9ds, a conversion code of STATE 4 is designated as the conversion code used for the next code conversion in this embodiment. In this case, in order to satisfy the RLL (2. 10) requirements, the first one bit or the first two bits of the conversion code of STATE 4 is xe2x80x9c1xe2x80x9d or xe2x80x9c0 1xe2x80x9d.
In this manner, a conversion code of STATE designated by the NS (the next STATE) added to each conversion code is used for the conversion of the next input code, so that the RLL (2.10) requirements can be always satisfied.
The code conversion section 82 comprises: an arithmetic unit 22 for calculating DSV (digital sum value), which will be described later; a comparator 24 for comparing DSV values; a memory (storage device) 28 for storing DSV value obtained up to the current conversion (to be described later) and STATE (NS) of the conversion code to be used for the next code conversion as described above; and a control section 26 for specifying STATE to be used in a next code conversion on the basis of the NS value of the memory 28 and converting the input code by controlling the arithmetic unit 22 and the comparator 24.
Wherever an input code is converted, the NS value (1, 2, 3 or 4) added to the conversion code is stored in the memory 28. According to the NS value stored in the memory 28, it is possible to specify which conversion code to be used among STATE 1 to STATE 4 for the next input code conversion.
In this manner, according to the NS value stored in the memory 28, it is possible to specify a conversion code to be used among a plurality of conversion codes (STATES 1 to 4) corresponding to an input code. However, as shown in FIGS. 11 and 12, there are two kinds of conversion codes corresponding to input codes of 0 to 87; one in a main table and the other in a sub-table. For this reason, either one of them needs to be selected. The conversion procedures in the case of input codes of 0 to 87 are different from those in the case of input codes of 88 to 255.
Where an input code is any one of 0 to 87, the corresponding conversion code is selected from either the main table or the sub-table. The selection of the conversion code is carried out by using the DSV values. As shown in FIG. 13, the DSV value is the integral of bit outputs whose polarity is inverted wherever xe2x80x9c1xe2x80x9d appears in the code. In the actual selection, the accumulated value of DSV values of conversion codes that have been used up to the current code conversion (hereinafter also referred to as DSV value obtained up to the current conversion). The DSV value up to the current conversion is calculated in the arithmetic unit 22 wherever an input code is converted, and then stored in the memory 28. The selection of the conversion code is carried out so that the DSV value up to the current conversion may approach zero.
Specifically, a conversion code can be specified by reading an NS value (a next STATE) from the memory 28 on the basis of the input code and STATE. A conversion code specified in the main table is read, and then a DSV value in the case of using this conversion code is obtained. This DSV value is obtained by adding the DSV of the conversion code itself to the DSV value obtained up to the current conversion. In the same manner, a conversion code specified in the sub-table is read, and then a DSV value corresponding to this conversion code is obtained. Thereafter, the two DSV values are compared, and the conversion code closer to zero is selected.
If the absolute values of the two DSV values are equal and the one closer to zero is not specified, the one having more number of polarity inversions is selected. If the numbers of polarity inversions are equal to each other, the one in the main table is selected. Thus, when the absolute values of the two DSV values are equal, a conversion code can be always selected from the main table without consideration of the number of polarity inversions, so that the process can be simplified.
Where an input code is in a range of 88 to 225, the corresponding conversion code is selected from the main table. In this case, however, when STATE 1 is specified on the basis of the NS value of the memory 28, the conversion code of STATE 4 may be used instead of that of STATE 1. In the same manner, when STATE 4 is specified, the conversion code of STATE 1 may be used instead of that of STATE 4.
In the selection of STATE 1 and STATE 4, a conversion code different from the originally specified conversion code is used, so that the converted code may not satisfy the RLL (2. 10) requirements in some cases. For this reason, when a different conversion code is used in place of the originally specified convention code, it is necessary to confirm whether or not the number of bits having a xe2x80x9c0xe2x80x9d value positioned between two bits having a xe2x80x9c1xe2x80x9d is two or more to ten or less. Where the different conversion code does not satisfy the RLL (2. 10) requirements, the originally specified conversion code is used. Alternatively, where the RLL (2. 10) requirements are satisfied, the selection of either STATE 1 or STATE 4 is made by using the DSV, in the same manner as the above-mentioned selection of either the main table or the sub-table in the case of an input code of 0 to 87.
Thus, in the conversion of the input code, a conversion code is read from the main table on the basis of an input code and an NS value of the memory 28, and then a DSV value in the case of using this conversion code is calculated. After that, when the input code is in a range of 0 to 87, a conversion code, which is a candidate for selection in the sub-table, is read, and a DSV value in the case of using this conversion code is calculated. When the input code is in a range of 88 to 225, the presence or absence of another selectable conversion code in the main table is checked. If there is a selectable conversion code in the main table, it is checked whether the selectable conversion code satisfies the RLL (2. 10) requirements. If the RLL (2. 10) requirements are satisfied, a DSV value in the case of using the conversion code is calculated. Thereafter, a conversion code is selected by comparing the DSV values.
Recently, the transfer rate of DVDs has been increased year by year, and the code modulation rate also. needs to be increased in accordance with the increase of the transfer rate. However, in the above-mentioned code modulator and modulation method, it is necessary to read codes twice from conversion tables. In addition to that, it is also necessary to check whether the read conversion code satisfies the RLL (2. 10) requiments, and to calculate the DSV in the case of using this conversion code. Moreover, there are also other problems. For example, the size of a conversion table becomes large and therefore a large area is occupied by the storage elements, and a large number of elements cause an increase in power consumption. In the conversion table 84 shown in FIGS. 11 and 12, the number of stored conversion codes is represented by:
256xe2x80xa2xe2x80xa24+88xe2x80xa2xe2x80xa24=1376.
It is an object of the present invention to reduce the size of a conversion table used for 8/16 code modulation.
It is another object of the invention to improve a transfer rate of a code.
These and other objects and advantages of the invention are attained in accordance with the principles of the present invention by providing a code modulator that converts an input code to one of a plurality of conversion codes. The present invention utilitizes a conversion table for storing conversion codes corresponding to input codes. Duplicate conversion codes are advantageously omitted from the plurality of conversion codes. A pre-processing table stores duplication information indicating a correspondence relationship between the conversion codes omitted from the plurality of conversion codes and the same conversion codes in the conversion table as the omitted conversion codes. A code specifying means specifies a conversion code to be used from the plurality of conversion codes, and a conversion code conversion means reads a conversion code corresponding to an input code from the conversion table on the basis of the specification done by the code specifying means and the duplication information stored in the pre-processing table.
In this code modulator, the conversion table stores conversion codes with duplicate conversion codes being omitted from the plurality of conversion codes. When the code specifying means specifies a conversion code stored in the conversion table, the code conversion means reads the specified conversion code. When the code specifying means specifies a conversion code omitted from the conversion table, the code conversion means reads the same conversion code as the omitted conversion code from the conversion table on the basis of the duplication information stored in the pre-processing table.
An aspect of the present invention provides a method for converting an input code to one of a plurality of conversion codes according to the present invention. According to this method a conversion code corresponding to an input code may be specified from among a plurality of conversion codes. Duplication information corresponding to the input code may then be read from a pre-processing table in which the duplication information indicating duplicate conversion codes in the plurality of conversion codes is stored. A conversion code corresponding to the input code can then be read from the conversion table which stores conversion codes with the duplicate conversion codes being omitted from the plurality of conversion codes on the basis of the code specification earlier performed and the duplication information read from the pre-processing table.
The code modulator and the code-modulation method according to the present invention makes it possible to downsize a conversion table. In addition, the present invention makes it possible to make a high-speed selection of either a conversion code specified to be used in the next code conversion and a conversion code specified to be used in place of the specified conversion code and a high speed checking of the RLL (2.10) requirements in the case of using a usable substitute of a conversion code.